NASA has demonstrated a resolve for a flagship mission in the coming years to revisit Venus and land instruments on the surface. Venus has a corrosive, high pressure (~100 bar), high-temperature (up to 500 C) environment presenting extreme design challenges for lander electronics. The ability to establish simple wire-line communications between circuits operating in extremely disparate temperature domains is a critical need. Different technologies have specific strengths (complexity, density, area, power) which span from high-performance, lower-temperature silicon to medium-density SiC-CMOS and lower-density, high-reliability SiC JFET-R. A viable lander design requires applying the right technology to each temperature domain. The premier IC process for ultra-high temperatures is the SiC JFET technology developed at NASA Glenn Research Center (GRC). In Phase I, Ozark IC proposes to use its extensive high temperature device and circuit expertise to create a PDK for the GRC SiC JFET process. Pre-existing designs by NASA will be recaptured with the PDK and simulation results will be validated against measured data. An RS-485 transceiver circuit will be designed using the PDK and verified such that it is ready for fabrication at the conclusion of Phase I.