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SBIR/STTR

Low Power 1-Bit ADC Array with Serial Output, Phase I

Completed Technology Project

Project Introduction

Low Power 1-Bit ADC Array with Serial Output, Phase I
Microwave interferometers for NASA missions such as PATH and SCLP consist of up to 900 receivers. Each receiver requires I and Q ADCs (analog-to-digital converters) for signal digitizing at >200MHz before further digital processing in the cross-correlators. Power dissipation as well as instrument volume and weight are the most important parameters in space born instruments. Pacific Microchip proposes designing a monolithic array consisting of 20x1-bit ADCs. A serializer will be integrated to reduce the number of outputs from 20 to 1. This will reduce the power per ADC and resolve the problem of wiring congestion where the cross-correlators interface. For further power reduction, Pacific Microchip proposes integrating a novel metastability programming feature into the ADC latches. The clock distribution will also be dramatically simplified. The 2-wire serial I²C (Inter-Integrated Circuit) interface will allow all 1800 ADCs to be calibrated and optimized. Phase I work will provide a complete definition, in silico validation of the product, and a hardware proof of concept. The Phase II program will produce a fieldable product. In order to facilitate the commercialization efforts in Phase III, a low cost commercial radiation-tolerant SiGe HTB technology will be used to fabricate the product. More »

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This is a historic project that was completed before the creation of TechPort on October 1, 2012. Available data has been included. This record may contain less data than currently active projects.

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