Small Business Innovation Research/Small Business Tech Transfer
A 45 nm Low Cost, Radiation Hardened, Platform Based Structured ASIC
Project Description
The proposed 45 nm radiation hardened platform based structured ASIC architecture offers the performance and density expected of a custom ASIC with the low manufacturing cost associated with a structured ASIC. The low cost, high performance customization of the structured ASIC portion of the chip is made possible by the 1-D 45 nm Mask-Lite process technology. The chip architecture is optimized for sensor data handling applications in space and the design process provides for a short development schedule. The architecture provides a hard macro microcontroller core with via-ROM program memory, SRAM data memory, CPU support logic, an appropriate set of analog functions, and a structured ASIC section for application specific functionality. A rad-hard by design logic cell library is provided for the structured ASIC area of the die along with a number of pre-compiled macro functions such as timers and serial I/O to reduce development time. The 1-D Mask-Lite process provides a dramatic reduction in the mask cost, allowing lower volume designs to gain access to 45 nm technology, and provides performance improvement over conventional via mask structured ASIC technologies by eliminating metal layer stubs. Standard logic design, verification and layout EDA tools are used to complete a chip design. The fixed microcontroller platform portion of the chip is implemented with optimized standard cells rather than the structured ASIC logic cells, resulting in standard ASIC performance levels for the core logic.
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Anticipated Benefits
Implemented with 45 nm 1-D Mask Lite radiation hardened standard cells, the proposed chip architecture is optimized for sensor data handling and actuator control applications in space or near-space environments. The hard macro analog and processor functions of the chip provide high performace processing comparable to a custom ASIC at a fraction of the cost, thereby supporting low volume designs which are processor based but need a significant level of custom logic to meet the mission needs. Built in analog and digital functions will provide for A/D conversion of analog inputs, standard serial interfaces to compatible sensors, SpaceWire interface to the intra-satellite network and actuator control support such as a multi-channel Pulse Width Modulation Timer. Exampe sensors would be velocity or position monitors, environmental sensors and imaging sensors. Actuator control is supported by circuits such as a multi-channel Pulse Width Modulated output Timer. Data processing is supported by a CPU with via ROM program memory for application specific code as well as the user customized structured ASIC logic which is ideal for implementing digital filters.
The proposed architecture implemented with non rad-hard standard cell libraries is optimal for low to medium volume processor based designs which require some custom logic and need the performance achievable in a 45 nm technology but do not have the volumes to justify the cost of a full custom ASIC. Verifying prototype or first generation designs before committing to a custom ASIC for high volume production is one market segment for this chip architecture and technology. Another is low to medium volume applications for sensor data processing and/or actuator control such as in industrial control and monitoring, medical equipment, and communication systems. Conversion of FPGA based designs to a structured ASIC for unit cost reduction and power/performance improvement is another significant target market. More »
The proposed architecture implemented with non rad-hard standard cell libraries is optimal for low to medium volume processor based designs which require some custom logic and need the performance achievable in a 45 nm technology but do not have the volumes to justify the cost of a full custom ASIC. Verifying prototype or first generation designs before committing to a custom ASIC for high volume production is one market segment for this chip architecture and technology. Another is low to medium volume applications for sensor data processing and/or actuator control such as in industrial control and monitoring, medical equipment, and communication systems. Conversion of FPGA based designs to a structured ASIC for unit cost reduction and power/performance improvement is another significant target market. More »
Primary U.S. Work Locations and Key Partners
| Organizations Performing Work | Role | Type | Location |
|---|---|---|---|
| American Semiconductor, Inc. | Lead Organization | Industry | Boise, Idaho |
Goddard Space Flight Center
(GSFC)
|
Supporting Organization | NASA Center | Greenbelt, Maryland |
Primary U.S. Work Locations
-
Idaho
-
Maryland
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This is a historic project that was completed before the creation of TechPort on October 1, 2012. Available data has been included. This record may contain less data than currently active projects.