Implemented with 45 nm 1-D Mask Lite radiation hardened standard cells, the proposed chip architecture is optimized for sensor data handling and actuator control applications in space or near-space environments. The hard macro analog and processor functions of the chip provide high performace processing comparable to a custom ASIC at a fraction of the cost, thereby supporting low volume designs which are processor based but need a significant level of custom logic to meet the mission needs. Built in analog and digital functions will provide for A/D conversion of analog inputs, standard serial interfaces to compatible sensors, SpaceWire interface to the intra-satellite network and actuator control support such as a multi-channel Pulse Width Modulation Timer. Exampe sensors would be velocity or position monitors, environmental sensors and imaging sensors. Actuator control is supported by circuits such as a multi-channel Pulse Width Modulated output Timer. Data processing is supported by The proposed architecture implemented with non rad-hard standard cell libraries is optimal for low to medium volume processor based designs which require some custom logic and need the performance achievable in a 45 nm technology but do not have the volumes to justify the cost of a full custom ASIC. Verifying prototype or first generation designs before committing to a custom ASIC for high volume production is one market segment for this chip architecture and technology. Another is low to medium volume applications for sensor data processing and/or actuator control such as in industrial control and monitoring, medical equipment, and communication systems. Conversion of FPGA based designs to a structured ASIC for unit cost reduction and power/performance improvement is another significant target market.