The unique characteristics of the proposed ADC array make it ideal for parallel digitizing applications that require power efficiency at high quantization rate. Oversampling can be used when more than 2-bit resolution is required. Such ADCs are critical components in multichannel wireless communication systems. Advanced ADC arrays are also required for neural implants, image sensors and sensor networks. The ADC array will be implemented using commercial 45nm SOI CMOS technology offering low device cost and extremely power efficient operation. The proposed Pacific Microchip Corp. Serializers and Deserializers (SerDes) capable of operating at a line rate of up to 32Gb/s are the essential blocks required for the next generation 100Gb/s (4x25Gb/s) Ethernet. We also plan to offer the ADC array as an IP block for integration in Systems On Chip (SoC). The extra-low power ADC arrays with serial outputs featuring power optimization capability depending on the required BER, high quantization frequencies, and convenient control through a two wire interface can be used in radiometer and interferometer instruments such as GeoSTAR. These instruments apply passive and active microwave technologies that are under development by NASA in its mission to provide inexpensive data for many different fields including science, agriculture, geology, weather forecast, climatology, and civil aviation. The potential application of the ADC arrays in space-based wireless communication systems promises to lower the cost of exploration data delivery to users.