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SBIR/STTR

Low Power 2-Bit ADC Array with Serial Output, Phase II

Completed Technology Project

Project Introduction

Low Power 2-Bit ADC Array with Serial Output, Phase II
Microwave interferometers for NASA missions such as PATH employ the GeoSTAR instrument, consisting of 600 receivers. Each receiver requires I and Q ADCs (analog-to-digital converters) for signal digitizing at 1GHz before further processing in the cross-correlators. Power consumption as well as instrument volume and weight are critical in space born instruments. During Phase I, Pacific Microchip Corp. designed the block diagrams and circuits of a monolithic array consisting of sixteen 2-bit ADCs. A serializer is integrated to reduce the number of outputs from 32 to 1. This reduces the power consumption per ADC and resolves the problem of wiring congestion in the interface with cross-correlators. For further power reduction, a novel metastability programming feature is integrated into the ADC latches. The clock distribution is fundamentally simplified as well. The 2-wire serial I2C (Inter-Integrated Circuit) interface allows all 1200 ADCs of the GeoSTAR instrument to be calibrated and optimized. Phase I work provided a complete definition and in silico validation of the monolithic ADC array with serial output. Phase II of the project will produce a fieldable product. In order to facilitate the commercialization efforts in Phase III, a Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Isolator (SOI) technology will be used for fabrication. More »

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