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SBIR/STTR

Rad-Hard and ULP FPGA with "Full" Functionality, Phase II

Completed Technology Project

Project Introduction

RNET has demonstrated the feasibility of developing an innovative radiation hardened (RH) and ultra low power (ULP) field programmable gate array (FPGA), called the RH/ULP FPGA. The design utilizes an advanced SOI process technology. It is the vision of RNET to develop a family of radiation hardened FPGA products with a variety of features including programmable logic, configurable analog functions, soft/hardcore microprocessor, dedicated DSP functions, I/O, dedicated memory blocks, memory controllers, global clock, and JTAG interface. In addition, specialized circuits for mitigation of TID/temperature effects, radiation hardened by design SEU techniques, and memory scrubbing are planned. Our vision at the conclusion of this proposed SBIR is to fabricate a "commercial" RH/ULP FPGA with the most important features listed. Ideally the FPGA to be developed under the proposed Phase 2 would contain all of these features, but due to the limitation of funds and allotted time, a scaled down version would be completed. The envisioned device will incorporate the basic programmable logic functions, dedicated block RAM, DSP functions, configurable I/O, global clock distribution network, and JTAG interface. Phase 2 will set the stage for more feature-rich product families to be developed as commercialization continues. More »

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