NASA's latest effort in developing a common platform for space communication and navigation systems is the Space Telecommunications Radio System (STRS) standard. It defines architecture enabling interoperability of Software Defined Radio (SDR) components. Future proof, power conscious architectures of STRS compliant re-configurable SDR transceivers are needed for implementation of envisioned space communication systems. Pacific Microchip Corp. proposes to develop a highly integrated, low-power, multifunctional 56GS/s Direct Digital Modulation/Demodulation (DDM) SDR transceiver using 45nm SOI CMOS technology. The resulting STRS compliant integrated solution will be radiation tolerant by technology and design. The direct conversion based transceiver utilizes novel 56GS/s D/A and A/D converters and features arbitrary waveform generation (AWG) mode. The availability of AWG and DDM modes removes limitations on the synthesized waveform shapes up to 28GHz. Pacific Microchip Corp. proposes all-digital implementation of frequency up- and down-conversion, I/Q modulation and demodulation. Since digital power is mostly dynamic, digital processing will enable power consumption scaling linearly with the operating frequency. Phase I work will provide a complete definition and in-silico validation of the proposed device. The Phase II program will produce a fieldable product. In order to facilitate the commercialization efforts in Phase III, a commercial radiation-tolerant CMOS SOI technology will be used.