Advanced reconfigurable/reprogrammable communication systems will require use of commercial sub 100 nm electronics. Legacy radiation tolerant circuits fail to provide Single Event Upset (SEU) immunity at speeds greater than 500 MHz. New base level logic circuits are needed to provide SEU immunity for high speed circuits afforded by sub 100 nm technology. A completely new circuit and system approach called Self Recovery Logic is proposed for development herein which is able to function at the full speed afforded by the fabrication process and able to tolerate SEU impacts not possible with legacy circuits. Moreover, a truly fault tolerant system is proposed which is projected to replace Triple Modular Redundancy as the on-chip means for fault tolerance. With the proposed building blocks in place, advanced reconfigurable and reprogrammable high speed devices can be implemented. A multiprocessor with advanced error correction and data compression capability is proposed for future development.