One of the key components in many NASA missions is a large-format focal plane Focal Plane Array (FPA) to capture images or 2 dimensional, hyperspectral information, especially in the Infra-Red (IR) domain. Apart from the detector, the performance of these FPAs is determined by the Read-Out Integrated Circuit (ROIC) that amplifies and multiplexes photo generated charge for signal processing by peripheral circuitry. In this project we propose to develop a new ROIC for low background applications, specifically designed to overcome present limitations of image persistence and inter-pixel capacitance (IPC). The main innovation in this project is an adaptive unit cell that can be individually and randomly programmed via on-chip logic to control bias state and reset duration of any pixel in the array while the integration of science data is on-going. In Phase I we will conduct a pixel trade study and performance evaluation for a Capacitive Trans-Impedance Amplifier (CTIA) and a source follower per detector (SFD) type pixel using analog circuit simulations. Then we will generate the optimum unit cell layout, define the overall architecture and create the top level schematic. By the end of Phase I we will have completed the blue prints for the design. The completion of the top level schematics, verified through simulation, is a critical milestone in the development. It substantially reduces the risk associated with creating new ROIC technology and will allow us to efficiently fabricate and test the device in Phase II. All results from Phase I will be documented in a preliminary Interface Control Document (ICD) so that the new ROIC can be considered for future missions. In Phase II we will produce the layout of the entire chip for fabrication using stitching lithography in a state of the art CMOS foundry and demonstrate its functionality on packaged prototypes. By the end of Phase II wafers of a known good ROIC design will be available for hybridization.