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SBIR/STTR

Robust, Wafer-level 3D Electrical Interconnect Technology, Phase I

Completed Technology Project

Project Introduction

There is a longstanding need for a reliable, low-cost manufacturing method for high-density three-dimensional (3D) interconnection of integrated circuits (ICs). This includes assembly of 3D stacked electrical interconnection of dissimilar semiconductors, electrical-interconnection of fine-pixel-pitch semiconductor detector arrays with readout ICs (ROICs) at the pixel level, and interconnection of ICs with flexible organic substrates and interposers. Such technology will allow for higher-density circuit integration into small-sized packages and enable high-density focal planes to be developed at lower costs. To address the need for high-density three-dimensional (3D) interconnection of circuits and detectors, including those made of dissimilar materials, inkjet-print additive-manufacturing (AM) materials and deposition technologies will be developed. It will be shown that reliable low-resistance electrical connections can be made- in three dimensions- to vertically stacked integrated circuits and interposers. The process is compatible with wafer-to-wafer, chip-to-wafer, and chip-to-chip processing, requires only modest capital investment, and can be performed with high yields at less cost and finer pitch compared to today's indium-bump hybridization technologies. In Phase I, the ability to produce densely packed conductive sub-1-μm and larger nanometal pillars to form low-resistivity 3D interconnects at a sub-3-μm pitch will be demonstrated. The process technology will be shown capable of forming 2.5D/3D stacked circuits at the chip and wafer levels. Parts will be electrically characterized over a range of frequencies, and samples will be environmentally and mechanically tested. More »

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Technology Maturity (TRL)

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