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SBIR/STTR

RFI mitigating receiver back end for radiometers, Phase I

Completed Technology Project

Project Introduction

This SBIR Phase I proposal requests support for Alphacore, Inc. to design and a low power application specific integrated circuit (ASIC) RFI mitigating receiver back end that can be incorporated into NASA's existing and future radiometer designs. Alphacore proposes next generation ASIC that provides significant SWAP reduction and better radiation hardness, as compared to board-level systems currently under development that use COTS ADCs and FPGAs. Alphacore ASIC will have a 3 GSPS (gigasamples per second), 12-bit, 340mW, radiation hard ADC and a 128-band, low-power digital filter bank. The total power consumption of the ASIC is less than one watt (0.87W). The ASIC will be developed in a small-geometry CMOS technology (28nm) that is inherently tolerant to high radiation doses. Single event effect mitigation strategies will be used as well in this ASIC. Alphacore has been developing IP in this process, including current mode logic (CML) transceivers and phase-locked loop (PLL) that can be leveraged in this program. The proposed system's front end ADC employs an innovative topology with a high-bandwidth front-end sampling circuit combined with an interpolated flash ADC and a back-end DSP that employs 128-band polyphaser filter bank using ultra low power synthesizable digital logic. The system is programmable and it is optimized to provide the user the most useful data available for effective RFI mitigation. The system is also designed to be scalable to other missions. More »

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