Ridgetop will develop a superior method for testing and qualifying columnar type of grid arrays such as field programmable gate arrays (FPGAs) packaged in column grid array (CGA) and ceramic column grid array (CCGA) packages using any type of manufacturing process. The proposed innovation is an electrical test method that utilizes unassigned CGA or CCGA package pins as dedicated monitoring pins, with a dedicated Solder Joint Built-in-Self Test (SJ BIST) program in the FPGA. SJ BIST operates in real-time to detect faults, with zero false alarms, in those connections. Supporting software provides a visual status of the state-of-health of each pair of monitored pins. At the end of the Phase 1, there will be a prototype HALT definition, a modified SJ BIST firmware designed specifically for use in HALTs (as opposed to being subjected to HALT for evaluation), a designed board with FPGAs programmed with the modified SJ BIST firmware, a prototype software program to support SJ BIST HALTs, at least two electronic boards fabricated and populated for use in developing and testing the software program. At the end of the Phase 2, the usefulness and accuracy of SJ BIST HALT will have been proven by the running of the defined HALT regimes. And by working with industry representatives, SJ BIST HALT will be ready for commercialization by government agencies, by suppliers of electronic boards to government agencies, by commercial firms.