High speed robust very low power radiation hardened bus interconnects are required to accelerate on-board computations, further improve reconfigurability and upgrade capabilities of tracking systems, and provide easy system upgrade. The existing radiation-hardening techniques significantly degrade the achievable circuit's performance, reducing speed and increasing power consumption. In order to accelerate on-board computations, improve onboard autonomous navigation and time-transfer systems that can reduce DSN tracking requirements, ADSANTEC will develop Multi-Gigabit Rate Radiation Hard Bus supporting an open system architecture and providing a cost effective multi-gigabit interconnect. This development will be based on ADSANTEC's pioneering SERDES concept, supporting a variety of interfaces and operating broadband at any frequency. The design will be based on ADSANTEC's proprietary patent pending library of radiation hardened cells based on HBTs with fT=120/220GHz and will be fabricated in a commercial high-performance BiCMOS technology. Phase I was devoted for bus architecture design and computer simulations of the synchronization circuitry. The complete chip will be fabricated at tested the end of Phase II, and space (Class K) qualified at Phase II. The proposed SERDES is a revolutionary upgrade of the existing ADSANTEC's Bus solution scheduled for launch (LADEE Program) in May 2011.