Current and future NASA missions are confronted with the challenge that the amount of data collected by its sensors significantly outpaces the down-link bandwidth. As a consequence, initial data reduction has to occur on-board, using algorithms sophisticated enough to sufficiently reduce the amount of data while simultaneously ensuring the preservation of valuable information. This requires enhanced processing power on-board the spacecraft/device/telescope. While future generations of rugged, radiation-hardened hardware can be expected to deliver the necessary performance by employing highly heterogeneous architectures consisting of a combination of FPGAs, DSPs and massively multicore architectures, software development for such devices poses a significant challenge. We prepose to develop tools that facilitate and accelerate algorithm development on these hardware devices. The tools will enable scientists to prototype algorithms in the High-Level language that they are most familiar with while simultaneously building code for high-performance computational hardware.