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SBIR/STTR

SEU/SEL Resistant Ultra-Low Power Asynchronous Processor Design for Low-Temperature Applications, Phase I

Completed Technology Project

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SEU/SEL Resistant Ultra-Low Power Asynchronous Processor Design for Low-Temperature Applications, Phase I
This Phase I SBIR proposal seeks funding to develop a radiation-hardened circuit architecture to achieve SEU and SEL immunity by using delay-insensitive asynchronous logic, and to demonstrate its feasibility, effectiveness, and efficiency. Further, early studies reveal that an operational temperature range of 2K to 400K will be highly feasible. Delay-insensitive asynchronous logic removes the concept of a global clock by incorporating handshaking protocols to control the circuit. The handshaking protocols allows for flexible timing requirements, high power efficiency, and low noise/emission generation. The flexible timing nature of delay-insensitive logic makes this type of circuits an excellent candidate for mitigating radiation effects in digital electronics. Compared to the existing radiation-hardening techniques, the proposed solution has several substantial benefits including cost efficiency, SEU/SEL immunity without weak points, and the ability to retain data during power cycling while mitigating SEL. In addition, significantly improved supply voltage variation sustainability and security against power-based side-channel attacks can also be achieved. More »

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This is a historic project that was completed before the creation of TechPort on October 1, 2012. Available data has been included. This record may contain less data than currently active projects.

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