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SBIR/STTR

High-Speed FPGA Image Decoder, Phase I

Completed Technology Project

Project Introduction

High-Speed FPGA Image Decoder, Phase I
NASA space imagery is gathered and transmitted back to earth in many formats. One of the newer formats is the lossy/lossless image format CCSDS (CCSDS 122.0-B-1), which uses wavelet decomposition combined with a bitplane encoder to achieve good data rates while keeping visual fidelity. It was designed for space missions, and in particular is designed to implement in low power hardware. This solicitation calls for creating a hardware solution capable of decoding 16-bit image samples from this format, called in this document the "CCSDS" image format, at the rate of 640 Mbps, presumably for ground based image acquisition systems. Cybernet teaming with University of Dayton Research Institute proposes to design and build a FPGA based hardware image decoder capable of decoding 16-bit samples with a rate at least 640 Mbps, which, given the specifics of the image specification, is completely feasible. Dr. Chris Lomont at Cybernet is currently PI on a project implementing precisely the CCSDS 122.0-B-1 specification and transcoding algorithms for a NASA Phase II SBIR, and is intimately familiar with the format. This coupled with Cybernet's long history of designing and delivering hardware solutions makes us a perfect fit for this project. More »

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This is a historic project that was completed before the creation of TechPort on October 1, 2012. Available data has been included. This record may contain less data than currently active projects.

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