The objective of the Phase-I research is to architect, model and simulate a multi-cluster Network on a Chip (NoC) reconfigurable Radio in SystemC RTL, with throughput up to 1Gbps. The architecture is based on mapping key Radio DSP operations onto clusters of 2D-Grid networks of primitive computation agents. The primitives in each cluster consists of multiply, accumulate and CORDIC operations. RISC agents and a primary RISC provide for reconfigurability. All agents are individually accessible for testing and configuration. The reconfigurable radio trades throughput for power by turning off primitive agents, using subsets of agents and routing links. Key agents that require SEU immunity for robust operation are identified and registers are implemented with Rad Hard temporal latch technology. The radio is reconfigurable for both beamforming and open-loop MIMO-OFDM operation with variable length FFTs to meet throughput/range requirements. The chip area and power is drastically reduced by maximum reuse of primitive agents by taking advantage of orthogonality between DSP operations. In Phase-II an NoC with support for 4x4 MIMO-OFDM will be synthesized on IBM 90nm process using Rad Hard agents and routing links that can be reconfigured for 4x1,4x2 and 4x4 MIMO-OFDM and single carrier operation, including FPGA emulation.