Skip Navigation
SBIR/STTR

Efficient Techniques for Formal Verification of PowerPC 750 Executables, Phase I

Completed Technology Project

Project Introduction

Efficient Techniques for Formal Verification of PowerPC 750 Executables, Phase I
We will develop an efficient tool for formal verification of PowerPC 750 executables. The PowerPC 750 architecture is used in the radiation-hardened RAD750 flight-control computers that are utilized in many space missions. The resulting tool will be capable of formally checking: 1) the equivalence of two instruction sequences; and 2) properties of a given instruction sequence. The tool will automatically introduce symbolic state for state variables that are not initialized and for external inputs. We bring a tremendous expertise in formal verification of complex microprocessors, formal definition of instruction semantics, and efficient translation of formulas from formal verification to Boolean Satisfiability (SAT). We will also provide formally verified definitions of the PowerPC 750 instructions used in the project, expressed in synthesizable Verilog; these definitions could be utilized for formal verification and testing of PowerPC 750 compatible processors, for FPGA-based emulation of PowerPC 750 executables, as well as in other formal verification tools to be implemented in the future. More »

Primary U.S. Work Locations and Key Partners

Project Library

Share this Project

Organizational Responsibility

Project Management

Project Duration

Light bulb

Suggest an Edit

Recommend changes and additions to this project record.

This is a historic project that was completed before the creation of TechPort on October 1, 2012. Available data has been included. This record may contain less data than currently active projects.

^