Direct imaging of exoplanets is key to fully understanding these systems through spectroscopy and astrometry. The primary impediment to direct imaging of exoplanets is the extremely high brightness ratio between the planet and its parent star. Direct imaging requires a technique for contrast suppression, which include coronagraphs, and nulling interferometers. Deformable mirrors (DMs) are essential to both of these techniques. With space missions in mind, Microscale is developing a novel DM with direct integration of DM and its electronic control functions in a single small envelope. The Application Specific Integrated Circuit (ASIC) is key to the shrinking of the electronic control functions to a size compatible with direct integration with the DM. Through a NASA SBIR project, Microscale, with JPL oversight, has successfully demonstrated a unique deformable mirror (DM) driver ASIC prototype based on an ultra-low power switch architecture. Microscale calls this the Switch-Mode ASIC, or SM-ASIC, and has characterized it for a key set of performance parameters, and has tested its operation with a variety of actuator loads, such as piezo stack and unimorph, and over a wide temperature range. These tests show the SM-ASIC's capability of supporting active optics in correcting aberrations of a telescope in space. Microscale has also developed DMs to go with the SM-ASIC driver. The latest DM version produced uses small piezo stack elements in an 8x8 array, bonded to a novel silicon facesheet structure fabricated monolithically into a polished mirror on one side and mechanical linkage posts that connect to the piezoelectric stack actuators on the other. In this Supporting Technology proposal we propose to further develop the ASIC-DM and have assembled a very capable team to do so. It will be led by JPL, which has considerable expertise with DMs used in Adaptive Optics systems, with high-contrast imaging systems for exoplanet missions, and with designing DM driver electronics. On its part Microscale will continue its design and fabrication of the ASIC-DM combination. Both the SM-ASIC and the DM are currently at a Technology Readiness Level (TRL) of 3; the major goal of the proposed effort is to raise the TRL of the combined system to 4 by scaling up the array formats and by testing, characterizing, and operating multiple generations of the integrated DM-ASIC systems in a laboratory environment. We propose a three year effort, with these tasks: Year 1: Optimize the influence function of an 8x8 DM for active / adaptive optics, by modeling and fabricating different geometric parameters of the facesheet, with its mechanical linkage posts. Fabricate an SM-ASIC and an 8x8 piezo stack DM, and evaluate their performance. Characterize and optimize the integration processes to achieve a driver/DM combination that can support high contrast imaging of exoplanets. Test the control resolution of the ASIC in driving actuators using a commercial interferometer, to ensure the ASIC can command the piezo stack actuator to nanometer levels. The goal, by year three, is control to a small number of picometers; 10-20 pm (surface) may be a practical goal, while 5 pm is the ultimate goal. Year 2: Fabricate 16x16 piezo stack DMs and matching driver ASICS, and repeat Year 1 tasks with the larger format devices. Year 3: Fabricate 32x32 DMs and SM-ASICs, and repeat Year 1 tasks with the larger format devices. Fabricate versions of the 32x32 devices that can be formed into a 2x2 array, to make a composite 64x64 DM/driver. Fabricate such a composite 64x64 DM/ASIC and evaluate its performance.