In this Phase II effort Toyon will increase the state-of-the-art for video/image systems. This will include digital image compression algorithms as well as system level integration, encompassing the image sensor all the way to compressed imagery data transport. To accomplish these goals Toyon will design a complete FPGA-based video compression system. The novel aspect of this design lies in the dynamically reconfigurable hardware IP cores that will interface to an embedded processor. Similar to a software defined radio (SDR) system where separate RF waveforms are loaded at runtime, Toyon aims to reload separate image compression encoders. This enables the use of several different image/video compression standards, all on the same hardware platform. The dynamically reconfiguring architecture of this system enables a single image sensor and hardware platform to handle the two most common space video camera applications, while still maintaining low power consumption in a highly integrated package. First, H.264 for high framerate, real-time video for situational awareness and surveillance. Second, lossless JPEG200 encoding for scientific and research post-processing. However, due to limited funds for this Phase II design, we will most likely work with a purchased H.264 IP core along with a standard JPEG compression core, which Toyon developed on the Phase I of this program. Providing the capability to reconfigure for both motion video and still image compression will provide near-term utility and demonstrate feasibility for Phase III development. Toyon will target the solution to a custom fully radiation hardened hardware platform. Potential radiation hardened components include a Xilinx FPGA, Xilinx PROM, Atmel SRAM memory, Aeroflex voltage regulators, and a Cypress CMOS image sensor paired with space-ready optics.