Wireless transceivers used for NASA space missions have traditionally been highly custom and mission specific. Programs such as the GRC Space Transceiver Radio System (STRS) seek to abstract the radio waveform from the hardware platform itself; this is meant to improve flexibility and promote component and subsystem reuse. In this Phase II effort Toyon proposes to perform work that will advance the state of the art in reconfigurable wireless transceivers in order to help realize the vision of STRS. Specifically, we propose to develop a modular, but highly integrated, digital and analog signal processing platform along with a standards-compliant waveform. The space-ready reconfigurable radio will serve a range of NASA missions and can be easily modified or enhanced for future needs. The RF front-end will be direct conversion with high integration of the frequency translation subsystems. For digital processing, we will pursue a system-on-a-chip (SoC) design with both reconfigurable logic and a soft-core processor implemented in a radiation-hardened Xilinx FPGA and PROM. The entire system architecture will leverage an EXP board-to-board connector design developed in Phase I. This system concept was validated in Phase I through Toyon's demonstration of a fully-functional packet-based 500 kbps waveform. In Phase II Toyon will pursue development of a waveform that is standards-based in order to further promote reuse and interoperability. Specifically, Toyon will develop a baseline implementation of the IEEE 802.16a standard. In addition to physical layer connectivity, such a waveform is well suited to IP-based networking, easing integration and increasing portability.