Supercomputing plays a major role in many areas of science and engineering, and it has had tremendous impact for decades in areas such as aerospace, defense, energy, finance, and telecommunications to name just a few. Supercomputing enables many of our most important high-tech tools, and nowhere is it more important than at NASA, where attaining increased computing speed and performance at lower costs are constant objectives. The goal of this multi-phase SBIR project is exactly that--to develop, validate, and commercialize next-generation supercomputing capabilities that provide NASA and other government/commercial users with massive increases in speed at minimal cost and with reduced energy requirements and significant "footprint" efficiency. In Phase I of this NASA SBIR project, Accelogic successfully demonstrated the feasibility of developing the world's first reconfigurable computing linear equation (banded) solver for large-scale computing problems--such as those seen in aerospace applications--with greatly increased speed using an FPGA chip. The speed attained was equivalent to 240 CPU's per FPGA chip for banded systems--which represents nearly a 60x computing speedup (surpassing the 50x Phase I target). Accelogic's Phase I success sets the stage for a Phase II effort focused on prototyping/validating an initial supercomputing acceleration product. The Phase II technical goal is to demonstrate the potential for 1,000x speedup. During Phase I, Accelogic has proven it is ideally positioned to capitalize upon recent advances in reconfigurable computing--many of which were attained by Accelogic's own experts. Applications for the products targeted by this project include many that are of interest to NASA, DOD, DOE, and many commercial entities. Based on Phase I results and the clear commercial potential, Accelogic has obtained interest/commitment letters from well-established commercial vendors and key NASA contractors, including Silicon Graphics.