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SBIR/STTR

Reconfigurable Computing for Dynamically Reprogrammable Communications, Phase I

Completed Technology Project

Project Introduction

Reconfigurable Computing for Dynamically Reprogrammable Communications, Phase I
This project addresses the need for a framework and domain architecture suitable for reconfigurable transceivers and associated component technologies. The goal of this effort is to provide flexible, reconfigurable communications capability while minimizing on-board resources and cost. WW Technology Group's (WWTG) approach provides a formalized structure for: (1) the design and implementation of reconfigurable computing (RC) using FPGAs for high performance parallel processing and (2) algorithm updates over the life cycle of the platform. In addition, this RC-Enabled approach can replace manual, ad-hoc development methods and support Runtime Reconfiguration (RTR) activities that allow the dynamic modification of the functional configuration of the RC hardware and adaptive computing. Specifically, WWTG's approach offers reconfigurable software and firmware that provides access control, and reconfiguration process including partial reconfiguration. The WW Technology Group (WWTG) presents a novel approach for reconfigurable, reprogrammable communication systems that provide high performance within the constraints of power consumption, reliability, size, and weight. By combining the system on a chip (SoC) technologies in a distributed platform supported by a flexible software infrastructure, our system strikes the optimal balance between size, power consumption, and functionality. More »

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This is a historic project that was completed before the creation of TechPort on October 1, 2012. Available data has been included. This record may contain less data than currently active projects.

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