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SBIR/STTR

Extremelly High Bandwidth Rad Hard Data Acquisition System, Phase I

Completed Technology Project

Project Introduction

Extremelly High Bandwidth Rad Hard Data Acquisition System, Phase I
Advancements in sensors/detectors are needed to support future NASA mission concepts including polarimetry, large format imaging arrays, and high-sensitivity spectroscopy. The corresponding data acquisition systems must employ high-speed, extra low power, linear analog-to-digital converters (ADCs) featuring a wide input bandwidth and reasonable effective number of bits, followed by a digital signal processor usually implemented inside a field-programmable gate array with a relatively low-speed data interface. In addition, radiation tolerance represents one of the main requirements for the space-oriented electronics. Commercially available ADCs feature high power consumption, high latency, poor linearity, and low radiation tolerance at high input bandwidths above 1GHz. To address the described needs, we propose a novel, low-power, high input bandwidth, radiation-tolerant, under sampling ADC with an output digital demultiplexer that enables direct data loading into a standard FPGA. Wide input bandwidth, low input return loss, 6-bit accuracy, low distortion and power consumption will be achieved through utilization of a proprietary adaptive matching filter and dual-output sample-and-hold amplifier followed by two reduced-rate ADCs. The digitized signals are delivered to the proprietary low-power LVDS output buffers after rate adjustment and realignment to the selected clock signal. Advanced technology featuring heterojunction bipolar transistors will provide the required radiation tolerance. More »

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This is a historic project that was completed before the creation of TechPort on October 1, 2012. Available data has been included. This record may contain less data than currently active projects.

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