Commercial digital signal processors (DSP) are problematic for satellite computers due to damaging space radiation effects, particularly single event upsets (SEU) and functional interrupts (SEFI). Space Micro has developed innovations for mitigating SEU and SEFI errors, enabling the use of very high-speed commercial DSPs with improved SEU tolerances (>1E-4 unrecoverable errors/day). Time-Triple Modular Redundancy (TTMR) is a method of applying traditional triple modular redundancy on a single processor, exploiting the VLIW class of parallel processors. SEFI is solved by a Hardened Core circuit, external to the microprocessor, which monitors the "health" of the processor, and when SEFI occurs, forces the processor to return to performance through a series of escalating events (interrupts, reset, etc). In Phase I we apply these technologies to COTS DSPs and also will extend the TTMR and Hardened Core architecture to reconfigurable FPGA arrays, with dramatically improved SEU/SEFI rates for Xilinx FPGAs. In Phase II we will provide SEU & SEFI hardened DSP plus FPGA product, with performance of 8,000 MIPS fixed point and 1.8 GFLOPS floating point (derated approximately 50% for improved SEU performance) while consuming less than 2 watts power, combined with an array of Xilinx reconfigurable FPGAs, providing approximately 7500 MFLOPS per FPGA.