The switching fabric (SF) is a key component of the next generation back plane interconnects. Extremely low-power, radiation-hardened, high-bandwidth upgradeable communication between computer nodes is of utmost importance for future NASA missions. The state-of-the-art binary SF interconnect architectures have high power consumption and low latency in order to perform internal data conversion and synchronization that allow for recognition of redundant bits and extraction of useful information from the data stream. The high power consumption of SF limits its application in the next generation nano-satellites. In order to minimize latency and reduce power consumption, we propose a novel, easy-to-align SF based on multi-level power-efficient Low Voltage Differential Signal interface. Our approach uses differential 3-level signals to mark a high-level reference bit position in one of the differential channels. Because the marked pilots follow the high-level logic in one of the differential outputs, they will regularly occur at the same bit position and ensure stable and easy recovery of the low-speed clock signal, which will be used as a reference for multi-channel data alignment and will synchronize a high speed clocking circuitry using a standard clock multiplier technique.