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SBIR/STTR

Software Redundancy Framework for COTS SoC FPGAs, Phase I

Completed Technology Project

Project Introduction

Redundancy is a powerful technique for achieving high levels of Single Event Upset (SEU) tolerance when utilizing commercial technology. While the multiple CPU cores boost performance by operating in parallel, they also can operate redundantly in order to maximize tolerance to SEUs. This approach requires a software framework to configure and operate the redundant system. In this proposed effort, Innoflight will develop a Software Redundancy Framework (SRF) for Commercial Off-The-Shelf (COTS) Multi-core System-on-Chip (SoC) Field Programmable Gate Arrays (FPGAs). The SRF is an IP core on an FPGA and associated software modules offering an elegant suite of targeted mitigations for SEUs, thus enabling COTS hardware to bring its superior SWaP to demanding radiation environments for the first time. We will examine the SRF: (a) initially with single-threaded user applications; (b) then with multithreaded applications; (c) testing with prototype hardware including under proton single event effects (SEE) testing; and (d) finally a potential flight demonstration on the ICE-Cap mission slated for launch in 2015. At the end of Phase II, Innoflight will have a complete framework that is ready for implementation on operational space computing platforms More »

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