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Small Business Innovation Research/Small Business Tech Transfer

Low-Cost, Manufacturable, 6-Inch Wafer Bonding Process for Next-Generation 5-Junction IMM+Ge Photovoltaic Devices

Completed Technology Project

Project Description

Low-Cost, Manufacturable, 6-Inch Wafer Bonding Process for Next-Generation 5-Junction IMM+Ge Photovoltaic Devices

To continue the trend towards ever more efficient photovoltaic devices, next-generation multi-junction cells will be based on increasingly complex structures. These structures will require the ability to join two or more independently grown epitaxial structures together via wafer bonding which is a complicated process to include in a high-volume manufacturing environment using conventional wafer fusion techniques. Additionally, metamorphic material is very difficult to bond due to the inherent roughness of the surface. We propose the development of a bonding process based on an epoxy interface with an embedded metallic grid to provide electrical conductivity across the bonded interface. This process is expected to be low-cost, compatible with metamorphic material and high-volume manufacturing, and readily scalable to 6-inch or larger substrates. It will be an enabling technology for next-generation, five- and six-junction solar cells with 1-sun AM0 efficiency exceeding 37% in high volume production. An example device structure that can benefit from the proposed wafer bonding technique is a six-junction solar cell. This six-junction device is composed of two triple-junction stacks, one of which is grown on a GaAs substrate while the other is grown on an InP substrate. The two triple-junction stacks must be bonded together to form the final six-junction device. The epoxy-bonding process proposed here will allow this bonding to be accomplished reliably on large-area substrates. This is essential for turning this structure into a practical, manufacturable, commercial product. When coupled with MicroLink Device's proprietary epitaxial lift-off (ELO) technology which allows for reuse of both the GaAs and InP substrates, devices based on this six-junction architecture could potentially be manufactured for less than $170/W in sufficient volume to serve near-term applications. This structure is expected to yield 40% efficiency under AM0 illumination.

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