Small Business Innovation Research/Small Business Tech Transfer
Radiation Hardened Structured ASIC Platform for Rapid Chip Development for Very High Speed System on a Chip (SoC) and Complex Digital Logic Systems, Phase II
Project Description
Radiation Hardened Application Specific Integrated Circuits (ASICs) provide the highest performance, lowest power and smallest size ICs for Space Missions. To dramatically reduce the development cycle, and reduce cost to tape out, Micro-RDC proposes a Structured ASIC approach. In this methodology, we fix an array of complex logic cells and provide a fixed area array for I/O pads supporting in excess of 400 Complementary Metal-Oxide Semiconductor (CMOS) General Purposes Input/Output (GPIO) pins. In addition, we fix the power grid and the pins associated with power (core and I/O) and ground. Thus, we require only routing in a subset of the metal layers to configure the Structured ASIC for a specific design. This leads to substantial reduction in design and verification time to tape out. Costs are reduced by requiring a subset of mask changes per design. In this work, we will build on Micro-RDC's existing 90nm silicon-proven Radiation Hardened Structured ASIC platform. We will develop a Structured ASIC platform at the 45nm SOI technology node. The objective is to increase clock speeds to hundreds of MHz. Single Event Upset (SEU) immunity is achieved in the sequential logic using Temporal Latch® Technology. We will provide turnkey Register Transfer Language (RTL) to GDSII capability for Radiation Hardened ASICs.
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Anticipated Benefits
With the rapid development cycle to manufacture packaged Radiation Hardened ASIC chips with the increased speed performance and dramatically lower power, NASA can enable interplanetary and long term low Earth orbit missions that support 32 bit and 64 bit System on a Chip (SoC) with high speed networking and multiple sensor bus support. These SoC ASICs will enable more complex sensor integration with Command and Data Handling (C&DH). Designs can be adapted to various bus protocols proposed and in use for CubeSat missions. The reconfigurable high gate count, multi-MHz SEU immune sequential logic, embedded RAM and mask programmable Read Only Memory (ROM) capability, allows for high performance processors to be designed to meet mission requirements in rapid production cycles with proven in silicon fabric and standard die I/O and robust high pin count packaging. The anticipated six month to silicon cycle will allow NASA the ability to meet mission schedules without sacrificing speed and power requirements and will also enable missions that were otherwise impossible to achieve in harsh radiation environments. Commercial companies that deploy geosynchronous satellites will benefit from the capability to design Radiation Hardened ASICs that can be configured in a rapid production cycle to meet specific demands for interfacing to communication systems over high band width busses. The dramatic cost reduction with Structured ASIC will make possible missions that required ASICs but were cost prohibitive. The Rad Hard Structured ASIC approach will also allow commercial CubeSat missions to extend beyond low Earth orbit to interplanetary missions that require greater Total Ionizing Dose (TID) and SEU immunity. Also commercial missions with high cost payloads can plan longer term low Earth orbit missions using Rad Hard, high performance, low cost ASICs in place of Commercial Off The Shelf (COTS) parts that will fail.
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Project Library
Primary U.S. Work Locations and Key Partners
| Organizations Performing Work | Role | Type | Location |
|---|---|---|---|
| Microelectronics Research Development Corporation | Lead Organization | Industry | Colorado Springs, Colorado |
Goddard Space Flight Center
(GSFC)
|
Supporting Organization | NASA Center | Greenbelt, Maryland |
Primary U.S. Work Locations
-
Colorado
-
Maryland
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