With the rapid development cycle to manufacture packaged Radiation Hardened ASIC chips with the increased speed performance and dramatically lower power, NASA can enable interplanetary and long term low Earth orbit missions that support 32 bit and 64 bit System on a Chip (SoC) with high speed networking and multiple sensor bus support. These SoC ASICs will enable more complex sensor integration with Command and Data Handling (C&DH). Designs can be adapted to various bus protocols proposed and in use for CubeSat missions. The reconfigurable high gate count, multi-MHz SEU immune sequential logic, embedded RAM and mask programmable Read Only Memory (ROM) capability, allows for high performance processors to be designed to meet mission requirements in rapid production cycles with proven in silicon fabric and standard die I/O and robust high pin count packaging. The anticipated six month to silicon cycle will allow NASA the ability to meet mission schedules without sacrificing speed and power requirements and will also enable missions that were otherwise impossible to achieve in harsh radiation environments.
Commercial companies that deploy geosynchronous satellites will benefit from the capability to design Radiation Hardened ASICs that can be configured in a rapid production cycle to meet specific demands for interfacing to communication systems over high band width busses. The dramatic cost reduction with Structured ASIC will make possible missions that required ASICs but were cost prohibitive. The Rad Hard Structured ASIC approach will also allow commercial CubeSat missions to extend beyond low Earth orbit to interplanetary missions that require greater Total Ionizing Dose (TID) and SEU immunity. Also commercial missions with high cost payloads can plan longer term low Earth orbit missions using Rad Hard, high performance, low cost ASICs in place of Commercial Off The Shelf (COTS) parts that will fail.