With the availability of small geometry SOI processes, STI has shown that it is possible to design and fabricate improved high performance, analog circuits with excellent rad-hard characteristics using Rad-Hard by Design and Process (RHBD and RHBP) techniques. STI has demonstrated rad hard design techniques by designing circuits using several SOI process for Phase I SBIRs including projects for the Air Force, the Navy and DARPA. STI proposes to use these proven techniques to demonstrate the feasibility of developing a Rad-hard ADC with 48ksps and 18 bit resolution using a 40nm SOI process from GlobalFoundries. The proposed architecture that Silicon Technologies Inc. proposes to implement, is a single loop, fifth order, Sigma Delta Modulator with a five bit Flash ADC for the quantizer. Designing analog circuits which are immune to radiation environments is difficult as ionizing radiation and even single ionizing particles can generate charges in semiconductor circuits. Previous research at STI successfully concentrated on the invention of an improved method to design rad-hard analog circuits called ADONIS. ADONIS is a structured approach which uses a cell matrix method where the designer places symbols representing circuit elements at locations that give optimum analog performance critical for small geometries. This allows a designer to view the schematic and layout simultaneously with immediate access to circuit parameters for SPICE simulations. In addition STI will use a new technique for maximizing the throughput of small geometry circuits for Ebeam Direct Write (EBDW). This new design technology called "1D" was invented by Dr. Michael Smayling, presently a consultant for STI. STI has developed an analog extension to the technology, Straight Line Analog, which will be used in this project. This technology has the benefit of providing EBDW at significantly smaller cost than previous whole wafer EBEAM in addition to improved manufacturing uniformity.