In this Phase II STTR project, RNET and its subcontractors are proposing to fully develop an empirical performance optimization tool called OrFPGA that efficiently explores the "user tunable" parameter space of an FPGA design and assists in deducing the near optimal design in terms of timing score, device utilization, and power consumption. The tunable parameter space will include IPCore parameters, HDL and HLS code constructs, and parameter settings for the vendor's design tools. Special automation tools will be developed to facilitate annotation of HDL/HLS code and design tool scripts. The computational magnitude of empirical performance tuning of FPGA designs will be addressed by novel machine learning based search algorithms requiring minimal empirical evaluations, computational steering, leveraging intermediate performance analysis results, and parallelization techniques. The tool will support specification of prioritized performance metrics, easy-to-use interfaces for defining the parameter space, and intuitive visualization of performance models. The user will be able to automatically deduce the best environment settings the chip and also accurately identify the optimal power consumption through optional real-time power monitoring. The benefits of the tool to NASA will be demonstrated in terms of performance metrics and cost benefits (user productivity) using real NASA designs that are used in space missions.