Skip Navigation
SBIR/STTR

Radiation Hard Monolithic SDRAM to Support DDR2 and DDR3 Architectures, Phase II

Completed Technology Project

Project Introduction

Space Micro has developed the architecture for a radiation hardened memory subsystem that targets DDR3-and-beyond generations of DRAM. The architecture combines server platform error correction and memory buffer-on-board schemes with Space Micro proprietary techniques for radiation hardening and size, weight, and power reduction. During the NASA Phase I effort, Space Micro demonstrated two key elements of the architecture: (1) a scalable error correction coding (ECC) scheme that optimizes the robustness vs. efficiency vs. chip count tradespace, and (2) a Rad Hard By Design (RHBD) timing circuit for advanced DRAM fly-by routing. Space Micro has developed a Phase II plan for developing a server platform-like bridge chip that integrates ECC, interface logic, and timing circuitry into a high performance, low size, weight, and power (SWaP) memory subsystem suitable for next generation spacecraft computing. More »

Anticipated Benefits

Primary U.S. Work Locations and Key Partners

Share this Project

Organizational Responsibility

Project Management

Project Duration

Technology Maturity (TRL)

Technology Areas

Light bulb

Suggest an Edit

Recommend changes and additions to this project record.
^