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Small Business Innovation Research/Small Business Tech Transfer

Radiation Hard Monolithic SDRAM to Support DDR2 and DDR3 Architectures

Completed Technology Project

Project Description

Radiation Hard Monolithic SDRAM to Support DDR2 and DDR3 Architectures, Phase II
Space Micro has developed the architecture for a radiation hardened memory subsystem that targets DDR3-and-beyond generations of DRAM. The architecture combines server platform error correction and memory buffer-on-board schemes with Space Micro proprietary techniques for radiation hardening and size, weight, and power reduction. During the NASA Phase I effort, Space Micro demonstrated two key elements of the architecture: (1) a scalable error correction coding (ECC) scheme that optimizes the robustness vs. efficiency vs. chip count tradespace, and (2) a Rad Hard By Design (RHBD) timing circuit for advanced DRAM fly-by routing. Space Micro has developed a Phase II plan for developing a server platform-like bridge chip that integrates ECC, interface logic, and timing circuitry into a high performance, low size, weight, and power (SWaP) memory subsystem suitable for next generation spacecraft computing. More »

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