The proposed low-power cross-correlator system is specifically targeted for NASA's PATH mission to process the GeoSTAR instrument's microwave sounder signals. The proposed system will digitize the signals at 1GS/s with 2-bit accuracy and will cross-correlate the IF (I and Q) signals of 3X128 receivers, located on the three arms of the Y-shaped antenna array. A total of 48 cross-correlator ASICs will be employed in order to implement the complete cross-correlation function required for the PATH mission. A novel cross-correlator system will allow to process these signals at greatly reduced power consumption, compared to the systems based on off-the-shelf components and FPGA. The proposed cross-correlator system, with some modifications, can also be applied in signal processing systems required for radio telescopes, such as the SKA that may employ more than 2000 receivers. The cross-correlators installed on such telescopes are projected to consume tens of kilowatts of power. Our system offers major reduction of power consumption. The proposed system's core will be made available as an IP core, which we will offer for implementation in other cross-correlators, employed in space-born and Earth-based NASA instruments. High energy efficiency at high data processing speed, radiation hardness and wide operating temperature range of the proposed cross-correlator system make it applicable in many space-based commercial and military systems to perform such functions as radiometry, interferometry, polarimetry, and spectrometry required for remote sensing applications. Low-power cross-correlators are also required for neural implants in medicine, for image sensor signal processing in military and homeland security, as well as for synthetic aperture radars in both military and civil aviation. The proposed system can be included into the signal-processing path of artificial eyes, ears or other sensory applications for signal processing, based on artificial neural networks. In order to ensure the highest outcome of the developed technology, the proposed system's core will also be offered as an IP block, which will be licensed to interested parties for a variety of applications that require fast and high energy-efficient parallel signal processing.