Develop a Universal Digital Processor Bus architecture using state of the art commercial packaging technologies.
This work will transition commercial advanced- yet mature- packaging approaches, such as surface mount and system-in-package, into mainstream use at JPL. Starting with an existing Digital Processor Unit (DPU) board that is planned to be used on multiple spacecraft in the next decade, we will apply modern commercial electronics packaging solutions to create a miniature version of the DPU. The DPU has multi I/O communication options (Spacewire, LVDS, 1553, TTE) and will target a 1U board form factor, down from existing 6U layout. Use performance COTS based devices to provide power and size reduction while maintaining performance and universal adaptability.
The DPU hardware will be used to demonstrate in-house manufacturability, cost effectiveness, functionality, performance, and reliability of state of the art electronics manufacturing and assembly for future-focused NASA missions. The implementation of newer packaging technologies will result in large decreases in mass, volume, and power of electronic subsystems.
Can shrink digital command board size by >40%. Improved signal and power efficiency has a positive effect on the entire flight system through reductions in IO count, cost, mass and volume. Improvement in manufacturing costs and increased reliability. Ready availability of components with shorter lead time and lower cost.More »
|Organizations Performing Work||Role||Type||Location|
|Jet Propulsion Laboratory (JPL)||Lead Organization||NASA Center||Pasadena, CA|