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SBIR/STTR

Rad hard Non volatile memory for FPGA boot loading, Phase I

Completed Technology Project

Project Introduction

Radiation-hardened non volatile memory is needed to store the golden copy of the image(s) has not kept pace with the advances in FPGAs. Consider that a single image of a Xilinx V5 typically is roughly 50 Mb large. If a designer wants to store several such images in a satellite, then a sizable amount of highly reliable, radiation-hardened memory is needed. As a consequence, there exists a clear need and market opportunity for highly reliable NVM for storing program code, calibration tables and images of reprogrammable FPGAs. The goal of this SBIR project is to develop a highly reliable and fault-tolerant, radiation-hardened Memory System-In-a-Package (Memory SIP) which can be used to configure and scrub reconfigurable FPGAs. The Memory SIP will contain a simple radiation-hardened microcontroller and a reasonable amount of commercial flash nonvolatile memory (NVM). It will support the needed standard interfaces that are commonly used for reconfiguring FPGAs, including Xilinx SelectMAP and JTAG. More »

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