NASA/JPL thermopile detector linear arrays, wire bonded to Black Forest Engineering (BFE) CMOS readout integrated circuits (ROICs), have been utilized in NASA missions such as the Mars Climate Sounder and the Diviner Lunar Radiometer Experiment. Linear array thermopile detectors are fabricated by bulk micro-machining. Surface micro-machined thermopiles are desirable for area array thermopiles because the architecture provides both high detector fill factor and circuit fill factor in the pixel. The Phase I effort designs an area array ROIC compatible with surface micro-machined thermopile detectors to meet requirements of future NASA thermal instruments requiring D-Star > 4 x 109 Jones. Radiation hard-by-design will be utilized with 180 nm CMOS for low 1/f noise readout, operating temp 77-300 K, radiation hardness and noise immunity with on-ROIC ADC. Various pixel pitches and binning methods will be investigated to cover a desired wavelength detection range of 20 µm 100 μm. The Phase I ROIC array design, in a 128x128 or larger format, will be fabricated on Phase II.