SBIR/STTR
Driver ASICs for Advanced Deformable Mirrors, Phase I
Project Introduction
The program leverages on our extensive expertise in developing high-performance driver ASICs for deformable mirror systems and seeks to expand the capacities of the proposed novel ASIC technology to beyond what have been possible by using traditional techniques. The overall goal of the SBIR program will be to develop a new class of Application Specified Integrated Circuit (ASIC) driver technology to be used in driver electronics of a deformable mirror (DM) system for reducing power dissipation, improving controllability, enforcing multiplexing bandwidth, and significantly reducing the form factors of the entire DM system for adaptive optics. Through the Phase I project, we aims to transform the technology readiness level from TRL 1 to TRL 2, and in Phase II, the technology readiness level for the proposed ASIC driver system will be promoted from TRL 2 to TRL 4 within a 2-year time frame.
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Anticipated Benefits
The driver ASIC and a DM will work together to enable NASA's applications including high-performance adaptive optics systems for (1) correction of aberrations in large-aperture, space-deployed optical interferometers and telescopes (e.g. for nulling coronagraph), (2) high-resolution imaging and communication through atmospheric turbulence, and (3) optical path alignment. Based on this NASA-supported ASIC driver platform technology, the products to be enabled through the program will be a series of driver ASICs for serving the deformable mirrors being used and/or to be implemented in NASA's future adaptive optics instrumentations. Not limited to the unique DM solution that our company is developing for NASA, but also applicable to drive DMs developed by other companies as long as the actuators are capacitive and within the working ranges of the driver ASIC. Differentiating itself from traditional driver solutions is its ultralow power dissipation, uncompromised board bandwidth (from quasi-static to up to 100 kHz), compactness, lightweight, and low cost, and should these features be demanded by a specific AO system design, the proposed ASIC technology will be worthy of considerations.
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Primary U.S. Work Locations and Key Partners
| Organizations Performing Work | Role | Type | Location |
|---|---|---|---|
Jet Propulsion Laboratory
(JPL)
|
Lead Organization | NASA Center | Pasadena, CA |
| Microscale, Inc. | Supporting Organization | Industry | Woburn, MA |
Primary U.S. Work Locations
-
California
-
Massachusetts
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Organizational Responsibility
Responsible Mission Directorate:
- Space Technology Mission Directorate (STMD)
Lead Center / Facility:
- Jet Propulsion Laboratory (JPL)
Responsible Program:
- SBIR/STTR
Project Management
Program Director:
Program Manager:
Project Manager:
Principal Investigator:
- Xingtao Wu
Project Duration
Start: May 2013
End: Nov 2013
Technology Maturity (TRL)
| Start: | 1 |
| Current: | 1 |
| Estimated End: | 2 |
Applied Research
Development
Demo & Test
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