Center Innovation Fund: JPL CIF
Ultra-Low Power Extreme Environment Capable Avionics System-on-a-Chip
Project Introduction
Develop ultra-low-power, wide-temperature (-150° C to +250 ° C), digital System-on-a-Chip (SOC) ASIC technology in a high resolution, inherently rad-hard IBM Silicon-on-Insulator (SOI) CMOS process to enable next-generation flight electronics. Demonstrate main flight-system electronics (flight processor, high- and low-speed instrument interfaces) in a chip containing a Cortex-M0 microprocessor that has been synthesized using a custom wide-temperature digital logic library developed in the same high resolution IBM SOI CMOS process.
More »Anticipated Benefits
The new SoC ASIC has a very good chance of setting NASA on a path to produce low-cost, ARM-based, SoC ASICs for avionics applications.
More »Primary U.S. Work Locations and Key Partners
| Organizations Performing Work | Role | Type | Location |
|---|---|---|---|
Jet Propulsion Laboratory
(JPL)
|
Lead Organization | NASA Center | Pasadena, CA |
Langley Research Center
(LaRC)
|
Supporting Organization | NASA Center | Hampton, VA |
Primary U.S. Work Locations
-
California
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Organizational Responsibility
Responsible Mission Directorate:
- Space Technology Mission Directorate (STMD)
Lead Center / Facility:
- Jet Propulsion Laboratory (JPL)
Responsible Program:
- Center Innovation Fund: JPL CIF
Project Management
Program Director:
Program Manager:
- Fred Hadaegh
Project Manager:
- Jonas Zmuidzinas
Principal Investigator:
- Ryan Stern
Project Duration
Start: Oct 2012
End: Oct 2013
Technology Maturity (TRL)
| Start: | 2 |
| Current: | 3 |
| Estimated End: | 3 |
Applied Research
Development
Demo & Test
Technology Areas
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