Develop ultra-low-power, wide-temperature (-150° C to +250 ° C), digital System-on-a-Chip (SOC) ASIC technology in a high resolution, inherently rad-hard IBM Silicon-on-Insulator (SOI) CMOS process to enable next-generation flight electronics. Demonstrate main flight-system electronics (flight processor, high- and low-speed instrument interfaces) in a chip containing a Cortex-M0 microprocessor that has been synthesized using a custom wide-temperature digital logic library developed in the same high resolution IBM SOI CMOS process.More »
The new SoC ASIC has a very good chance of setting NASA on a path to produce low-cost, ARM-based, SoC ASICs for avionics applications.More »
|Organizations Performing Work||Role||Type||Location|
|Jet Propulsion Laboratory (JPL)||Lead Organization||NASA Center||Pasadena, CA|
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