Development of a Low Mass, Low Power Deformable Mirror with Integrated Drive Electronics

Deformable mirrors (DM) are key to achieving high contrast for any mission to image expolanets. Currently Northrup Grumman Xinetics is the only viable source for high-contrast capable deformable mirrors. This proposal will help to develop a deformable mirror with integrated driver electronics, eliminating traditional bulky external driver electronics and the associated cabling. The DM will have reduced mass and volume and will consume less power than traditional DMs. "Deformable mirrors (DM) are key to achieving high contrast for any mission to image expolanets. Currently Northrup Grumman Xinetics is the only viable source for high-contrast capable deformable mirrors. This proposal will help to develop a deformable mirror with integrated driver electronics, eliminating traditional bulky external driver electronics and the associated cabling. The DM will have reduced mass and volume and will consume less power than traditional DMs. In addition to the reduced mass and volume, the approach incorporates a number of innovations to improve overall DM performance. The actuator uses single crystal giant-piezos offering up to 10 times the energy density of conventional ceramics, and a force-focused and cantilevered configuration to maximize the transducers energy efficiency in generating mirror motions. In addition, it utilizes a bulk micromachining process for DM fabrication in order to create a single crystal architecture at low cost and with a high optical quality surface figure. When fully developed, the DMs are expected to have large stroke (8-um), low-voltage (~40V), low weight, fast rise time (10 microseconds) and low manufacturing cost. Our price/performance goal is 10,000 actuators with a 10 kHz framing rate for $40k. The technology is scalable from hundreds of actuators to millions of actuators. Microscale delivered a first generation DM to JPL under an SBIR grant in early March 2011. This first generation DM driver was delivered with a simple Microchip-based serial interface from the ASIC to a control computer, and detailed documentation on the ASIC interface protocol. JPL will develop an FPGA high-speed ASIC/computer interface, one capable of operating the DM at its full frame rate. Once the high-speed DM driver is complete, JPL will characterize the delivered 32x32 DM in the lab. We will measure the frame rate of the DM, actuator response speed, maximum stroke, go to positioning accuracy, number of dead ac More »