The objective of this project is to investigate RISC-V soft-core processors and demonstrate their capability for flight by integrating them into the SpaceCube v3.0 Mini (SC3-Mini), which features a Xilinx UltraScale FPGA. With complex, next-gen sensors producing ever-increasing volumes of data, there is a growing need for high-performance, reliable onboard processing capabilities that the SC3-Mini offers to provide data reduction/compression, onboard product generation, automated health and status monitoring, etc. However, the proprietary MicroBlaze soft-core processor traditionally used on SC3-Mini has significant limitations due to its antiquated architecture, restricted configurability, and limited adoption in industry. Therefore, this project aims to explore open-source RISC-V soft-core processor implementations, which can leverage a widely-adopted and growing hardware/software ecosystem that is able to construct highly configurable processors to meet the variety of mission requirements.
Additionally, the RISC-V ecosystem supports a variety of specialized computational units capable of speeding up intensive workloads such as Artificial Intelligence and Machine Learning tasks. This project will investigate several of these accelerators, including the Gemmini systolic array generator and NVIDIA Deep Learning Accelerator, and build them into integrated solutions capable of running on the SpaceCube platform.More »
The transition from the proprietary MicroBlaze architecture on SpaceCube v3.0 Mini (SC3-Mini) to open-source RISC-V will be a critical step in expanding NASA’s on-orbit computational capabilities, allowing the SC3-Mini to accommodate a variety of computational needs for different missions. Novel RISC-V processors implementations, such as Rocket Chip, have numerous advantages over the current MicroBlaze implementation on the SC3-Mini from both hardware and software perspectives. From the hardware point-of-view, Rocket Chip offers enhanced performance and configurability. More specifically, the MicroBlaze processor is only single core, though this core can be configured in a variety of ways with respect to cache size, pipeline stages, memory management units, etc. In contrast, the Rocket Chip RISC-V processors can be customized to 1, 2, 4, and 8 cores with 32- or 64-bit architectures and varying cache and memory bus width sizes. Therefore, for missions requiring high-performance and parallel processing, a multicore RISC-V can be implemented, while for missions requiring relatively less processing power, a single-core RISC-V implementation can be used to save on resource utilization and power. Furthermore, the RISC-V instruction set architecture (ISA) is highly extensible, allowing for custom instructions to be implemented in the microarchitecture. This feature provides the means for the tight integration of custom hardware accelerator engines to increase processing speed for application-specific algorithms for onboard science data processing. From a software perspective, the rapid adoption of RISC-V has also led to an ever-growing open-source community that continues to create software and enable support for RISC-V, which significantly exceeds the community developing for the proprietary MicroBlaze. Moreover, because the base instructions in the RISC-V ISA are standardized and fixed, software developers can guarantee long-term code portability even as the microarchitecture evolves with new extensions. This long-term portability is critical for NASA missions that can span years or even decades and thus require the support of legacy flight software.More »
|Organizations Performing Work||Role||Type||Location|
|Goddard Space Flight Center (GSFC)||Lead Organization||NASA Center||Greenbelt, Maryland|