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Center Innovation Fund: LaRC CIF

Neuromorphic UAS Collision Avoidance

Completed Technology Project

Project Introduction

Collision avoidance for unmanned aerial systems (UAS) traveling at high relative speeds is a challenging task. It requires both the detection of a possible collision and deployment of an appropriate maneuver to avoid it, to be done in few seconds or less. NASA Langley and Boston University are engaged in a collaborative effort to design neuromorphic optic flow algorithms to avoid collisions and embed these algorithms in small, low-weight, and low-power customized hardware solutions in UAS.

Using biologically-inspired neuromorphic optic flow algorithms is a novel approach in collision avoidance for UAS. Traditional computer vision algorithms rely on solving nonlinear partial differential equation systems to estimate optic flow which is a computationally expensive task. Neuromorphic algorithms instead make use of lessons learned in biology to solve these problems in a more efficient manner. An example is the fly's motion detector, which can be modeled by a system that uses a set of locally calculated, parallel spatio-temporal correlations for a set of velocities determined by the input sampling rates and flying speeds. Correlation results are interpreted as likelihood for a motion direction and speed. Stages of obstacle detection and tracking can temporally and spatially integrate these likelihoods to increase the signal-to-noise ratio, and in turn the detection rate. In addition to its computational efficiency, the proposed neuromorphic solution is more stable and noise tolerant than solving a nonlinear optimization problem. Even if single computational nodes get corrupted due to functional or structural failures in the hardware, the performance of appropriately designed parallel, distributed neuromorphic algorithms degrades gracefully. Neuromorphic algorithms are commonly implemented using software running on general-purpose multicore/graphic processing unit systems. This approach, though flexible, can have significant overhead in terms of power, performance, and is not easily portable across platforms, therefore reducing its scope of applicability. In the second phase, we will port the neuromorphic algorithms to field programmable gate arrays (FPGAs) and application specific integrated chips (ASICs). This will allow us to meet demanding performance requirements needed in UAS such as fast processing, low weight, low power consumption, as well as robustness to hardware failure.

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Technology Maturity (TRL)

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