Two primary paths are available for the creation of a Rad-Hard ASIC. The first approach is to use a radiation hardened process such as existing Rad-Hard foundries. These foundries use special processing steps to decrease the total ionizing dose issues, but do not reduce the single event effects. The second approach is to use a special standard cell library containing hardening techniques that can be built on a standard state-of-the-art commercial foundry. This cell library must compensate for the unhardened foundry by using special layout techniques to retain the ability to operate through the total ionizing dose experienced in the radiation environments. These techniques are generally referred to as radiation hardened-by-design layout techniques (RHBD). For hardening of the circuit architectures against upsets from the single event effects, both the commercial and the Rad-Hard foundries must incorporate some type of mitigation scheme requiring special transistor interconnects or redundant nodes. This program will fill this void, providing the space community with the ability to easily acquire the RHBD Micro-RDC standard cell libraries for use with commercial ASIC design flows. The library will include a full suite of IO pads designed by Micro-RDC and successfully implemented in test chip designs at 90nm and 65nm. Finally, a portion of the custom via programmable structured ASIC fabric designed by Micro-RDC and Viasic will be made available to the library users. This fabric can be embedded into a design which can be modified and reprogrammed by generating just via 3 mask layer, which can lead to a substantial cost savings over a complete new ASIC design. This program will allow Micro-RDC to transform its custom libraries into synthesis libraries, and enable other companies the opportunity to use a proven and fully characterized RHBD ASIC cell library and suite of Mega Cell hard IP for rapidly developing spaceborne systems.