Space Technology Research Grants
A Circuit-Level Radiation Hardened-By-Design Approach for Standard CMOS
Project Description
The primary objective of the research inquiry is to validate a circuit-level radiation hardening technique for digital and mixed-signal electronics. Computer simulations have indicated that the technique works; however, there have been no published experimental results validating it. To complete the primary objective, there are plans to experimentally validate the hardening technique and to quantify its effectiveness and any performance degradation introduced by it. In comparison with many device-level hardening techniques, this circuit-level technique may reduce the development time and costs of digital or mixed-signal electronics in craft bound for radiation-rich environments such as space.
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Anticipated Benefits
In comparison with many device-level hardening techniques, this circuit-level technique may reduce the development time and costs of digital or mixed-signal electronics in craft bound for radiation-rich environments such as space.
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Primary U.S. Work Locations and Key Partners
| Organizations Performing Work | Role | Type | Location |
|---|---|---|---|
| The University of Tennessee-Knoxville (UT-K) | Lead Organization | Academia | Knoxville, Tennessee |
| Jet Propulsion Laboratory (JPL) | Supporting Organization | FFRDC/UARC | Pasadena, California |
Primary U.S. Work Locations
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Tennessee
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