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SBIR/STTR

Stackable Radiation Hardened FRAM, Phase II

Completed Technology Project

Project Introduction

Stackable Radiation Hardened FRAM, Phase II
Purpose of this effort was to offer a novel solution to the pressing need for radiation tolerant memory for the demanding satellite and space probe worldwide community. The effort included radiation testing of the Ferro Electric Random Access (FRAM) memory developed under NASA/JPL contract NNG04CA25C, and the design of stacked versions resulting in up to 16Mb of storage in a footprint smaller than a standard TSOP. The work done resulted in a number of tested samples of 2Mb FRAM die fabricated using the 0.35 um process at Fujitsu, and designed by Cellis Semiconductor. The packaged parts were electrically tested then subjected to radiation testing. The enclosed radiation test program conducted and the successful results are contained herein. For higher density configurations, a preliminary design of stacks in 2, 4, and 8 high die was done using our ┬ÁZ Ball StackREG technology, offering a total of up to 16Mb of addressable memory. More »

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This is a historic project that was completed before the creation of TechPort on October 1, 2012. Available data has been included. This record may contain less data than currently active projects.

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