Excitonics Based on Carbon Nanomaterials: a Pathway Toward Low-Power, High-Speed, and Radiation-Hard Computation

a. Introduction Scaling in silicon complementary metal-oxide semiconductor (CMOS) technology has followed Moore’s law, which predicts doubling of transistor density every two years, for the past 40 years. 1 These sustained advances have facilitated phenomenal innovation in both terrestrial and space-based electronic systems. However, as device dimensions approach the 10 nm length scale conventional CMOS fabrication techniques will increasingly face both technological and fundamental challenges, such as short-channel effects, parasitic resistance and capacitance, and power management, 2–5 that will limit the historical benefits of scaling. To continue performance increases in next generation electronics, alternative device geometries and technologies, such as excitonic logic switches, are being pursued. 5,6 Excitons, which are bound electron-hole pairs with a net zero charge, have the potential to be utilized in high-performance logic switches that operate at 1000 times lower power than conventional CMOS field-effect transistors (FETs). 7 Previously, exciton-based devices have been demonstrated in compound semiconductor quantum wells, but the exciton binding energy is small in these materials (~10 meV) and they can only operate at cryogenic temperatures. 8 Alternatively, one-dimensional (1D) carbon-based nanomaterials (e.g., carbon nanotubes and graphene nanoribbons) possess attractive excitonic properties including binding energies greater than 0.1 eV (indicating they could be used in room-temperature applications) and long radiative lifetimes.7 Additionally, excitons in these 1D systems are predicted to vary as a function of single-walled carbon nanotube (SWCNT) structural parameters (e.g., diameter and chirality) and graphene nanoribbon width, which could allow for tunable nanoelectronic systems. 9,10 As exciton technologies mature, there will be demand for them in both terrestrial and space based systems. While both environments will require high-performance, low-power electronics, increased radiation-tolerance is essential for space electronic systems because they operate in environments that contain large amounts of ionizing radiation, which can lead to radiation induced damage in the system.11 One way ionizing radiation can degrade electronic systems is through single event effects (SEEs). Typically, these effects occur when a single charged particle interacts with the semiconducting and insulating materials in a device and liberates electrons from the constituent atoms, leading to behaviors such as a single event transient. 6 Other forms of radiation-induced damage in electronic devices are the so-called long-term effects, displacement damage dose (DDD) effects and total ionizing dose (TID) effects. DDD effects result from the displacement of nuclei from their lattice position, which reduces device performance. 12 On the other hand, TID effects in electronic systems primarily affect the dielectric material because ionizing radiation can generate trapped charges which shift threshold voltages and increase low frequency noise. 13 Carbon nanomaterials and molybdenum disulfide (MoS2) have been studied extensively for next generation electronics because they exhibit unique properties, and offer the opportunity for ultimate scaling.14–16 They are also promising for use in radiation environments because their small target cross-section could lead to an increased resistance to DDD effects via ionizing radiation17–19. These nanomaterials are being increasingly combined with high-k gate dielectrics, such as self-assembled nanodielectrics (SANDs), to achieve high capacitance without reducing oxide thickness. Preliminary investigations suggest SANDs have some radiation-tolerance to high energy proton and photon irradiation, but these effects have not been thoroughly characterized20. Therefore, the unique properties of carbon nanomaterials, MoS2, and SANDs suggest opportunities for ultralow power and radiation-tolerant logic devices necessary for next generation commercial and space nanoelectronic applications. This interdisciplinary project joined novel semiconducting (SWCNTs, graphene, and MoS2) and dielectric materials (SANDs) with advanced lithographic techniques, noise spectroscopy, and radiation testing to study the science and device potential of nanoelectronics for space applications. Specifically, low-frequency noise and TID effects were explored through the following research objectives: 1. Completing low-frequency noise testing on MoS2 field-effect transistors 2. Investigating low-frequency noise in graphene field-effect transistors 3. Testing the radiation resistance of semiconducting nanomaterials and SANDs with ionizing radiation sources b. Low-Frequency Noise Electronic Noise in Single-Layer MoS2 Field-Effect Transistors In this project, we analyzed low frequency (1/f) conductance fluctuations in high mobility (up to 65 cm2/Vs at room temperature) single-layer MoS2 (SL-MoS2) FETs. We observed that 1/f noise in SL-MoS2 FETs follows Hooge’s empirical law in the accumulation regime (i.e., when the gate voltage (Vg) is larger than the threshold voltage (Vth)) with a Hooge parameter varying from 0.005 to 2.0 in vacuum (< 10-5 Torr). The lowest values of the Hooge parameter are similar to other “all-surface” nanomaterials such as CNTs on oxide gate dielectrics, which indicates dielectric quality is a large factor determining the 1/f noise level. Moreover, the noise amplitude scales linearly with the total number of carriers in FETs fabricated on single MoS2 flakes, veryifying that 1/f noise is due to fluctuations in carrier mobility and not fluctuations in the number of carriers.20, 21 We also measured the low-frequency noise in SL-MoS2 FETs in ambient as well as under reduced temperature. Under ambient conditions, the Hooge parameter and noise amplitude increased by an order of magnitude, which highlights the significant influence of atmospheric adsorbates on SL-MoS2. Additionally, the Hooge parameter shows an inverse relationship with field-effect mobility (μFET) in a manner similar to organic thin-film transistors22 and graphene FETs.23 When the devices were cooled from 300 K to 6.5 K, generation-recombination (GR) noise24 was observed. This GR noise could be due to traps in the underlying SiO2 substrate or midgap states in SL-MoS2, indicating noise spectroscopy could be a unique diagnostic tool for analyzing trapping processes and materials purity in ultrathin semiconductors. Finally, these noise metrics are expected to provide practical guidelines for the development of high performance electronic and sensing devices based on single-layer transition metal dichalcogenides. c. Reducing Flicker Noise in Chemical Vapor Deposition Graphene In this project, we achieved an order of magnitude reduction of 1/f noise in chemical vapor deposition (CVD) graphene FETs (G-FETs) by avoiding water-based processing chemistry. The area-normalized noise spectral density (10-7 – 10-8 µm2Hz-1) is comparable to high-quality exfoliated graphene and Si-based MOSFETs at similar carrier density.25 Furthermore, the unusual linear energy dispersion in SL graphene resulted in a unique dependence of the 1/f noise characteristics on carrier density. In particular, we observed V-shape, M-shape, Λ-shape, or weak/no-shape dependencies of the noise on carrier concentration, which varied with sample quality and processing conditions.25 Our highest performing CVD graphene devices show an M shape dependence on carrier density that has been previously observed only in high quality exfoliated graphene,26,27 bilayer graphene,27 and suspended graphene.27 Since no obvious correlation was found between the noise amplitude and gate bias dependence, both Hooge’s mobility fluctuation and correlated carrier-mobility fluctuation models were used to describe the qualitatively different behaviors observed in these devices. Using these models, we determined the overall reduction of noise in these devices is due to a decrease in the configurational noise, which is achieved by quenching dynamic redistribution of interfacial disorder. Moreover, the lack of correlation between the Hooge parameter and the carrier mobility suggests that additional improvements in CVD growth to minimize crystal defects are unlikely to produce quieter graphene devices. Instead, strategies that have been employed to reduce the noise in high-quality exfoliated graphene would likely also benefit CVD graphene devices. d. Tunable Radiation Response in Organic-Inorganic Hybrid Gate Dielectrics for LowPower Graphene Electronics In this project, we examined TID effects in low-power, high performance CVD G-FETs employing zirconium oxide (ZrOx)-based SANDs (Zr-SAND). Zr-SAND is comprised of alternating layers of ZrOx and a highly polarizable phosphonic acid-based π-electron stilbazolium molecule.28,29 This multilayer structure offers precise thickness control (~1 nm), low leakage current density (~10-7 A/cm2 ), and high capacitance (up to 750 nF/cm2) in an ambient atmosphere.28 We irradiated these devices with a vacuum ultraviolet (VUV) irradiation source, and observed increased negative charge density in the dielectric. To decouple the radiation induced mechanisms within Zr-SAND, we irradiated G-FETs employing a neat ZrOx dielectric. Specifically, a radiation-generated competing charge trap population was observed in ZrOx, as indicated by gate bias polarity dependent shifting in the transfer curves and asymmetric hole and electron mobility degradation. From these measurements, we deduced the organic layer accumulates negative charge density following irradiation. The competing intra- and interlayer charge trapping mechanisms in Zr-SAND imply the overall response can be changed by varying layer thicknesses, which we demonstrated in hybrid proof-of-concept devices. Therefore, this study suggests SAND layer thickness tuning offers unique opportunities to tailor the radiation response of graphene electronics, with potential applications ranging from dosimeters to radiation-tolerant electronics.